1. Field
Exemplary embodiments of the present invention relate to a buffer circuit that senses and amplifies an input signal and drives the amplified signal.
2. Description of the Related Art
A buffer circuit adopted as an interface circuit in a semiconductor device such as a semiconductor memory plays an important role of receiving and buffering a signal applied from outside and transferring the buffered signal to an internal circuit of a chip.
FIG. 1 is a diagram showing a conventional buffer circuit.
Referring to FIG. 1, the buffer circuit includes an amplification unit 10 which amplifies an input signal IN and a driver 20 which pull-up drives or pull-down drives an output node in response to an amplified signal PRE_OUT. The driver 20 may be constituted by an inverter. The amplification unit 10 amplifies the difference between the input signal IN and a reference voltage VREF and outputs the amplified difference as the amplified signal PRE_OUT to the driver 20. The driver 20 inverts the amplified signal PRE_OUT and outputs a resultant signal to an internal circuit of a chip.
If an offset occurs in the reference voltage VREF, the duty of the signal PRE_OUT outputted from the amplification unit 10 may become unbalanced. That is to say, the high pulse width and the low pulse width of the output signal PRE_OUT of the amplification unit 10 may become different from each other. This will be described below with reference to FIG. 2.
FIG. 2 is a waveform diagram of the buffer circuit shown in FIG. 1.
FIG. 2 exemplifies that the reference voltage VREF is increased by a positive (+) offset OFFSET. Although the ratio between the high pulse width and the low pulse width of the input signal IN have been balanced to be 1:1, as the positive (+) offset OFFSET occurs in the reference voltage VREF, the high pulse width of the output signal PRE_OUT of the amplification unit 10 decreases, and the low pulse width of the output signal PRE_OUT of the amplification unit 10 increases. In other words, the duty of the output signal PRE_OUT of the amplification unit 10 becomes unbalanced. As the output signal PRE_OUT is inverted by the driver 20, in a signal OUT loaded on the output node, the high pulse width becomes longer than the low pulse width. Namely, the duty of the signal OUT loaded on the output node becomes unbalanced as well.
In this way, in the conventional buffer circuit, if the offset OFFSET occurs in the reference voltage VREF inputted to the amplification unit 10, the duty of the signal OUT loaded on the output node becomes unbalanced. If the duty of the signal OUT becomes unbalanced, the integrity of the signal OUT may deteriorate and data may be recognized incorrectly.